Increasingly lower-power semiconductor structures are needed to reduce power requirements of integrated circuits, such as memory devices. Memory devices, such as SRAMs (Static Random Access Memories), are typically implemented using bitcells, whose performance is a function of many parameters including semiconductor techniques used to implement the bitcells. SRAM bit cell functionality and performance, among other things, depends on the write margin of the bit cell. Higher write margin enables one to change the state of a bit cell using a lower voltage. Lower voltage correspondingly results in lower power consumption by the bit cell and thus the memory using the bit cell. However, conventional memory devices require higher voltage to perform a state change of the bit cell resulting in higher power consumption. Thus, there is a need for an improved transistor structure that results in a higher write margin for bitcells without degrading read performance for memory devices, such as SRAMs.
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